CONFIG PREEMPT RT Patch
The CONFIG_PREEMPT_RT Patch Set
The CONFIG_PREEMPT_RT patch set is maintained by a small group of core developers, led by Ingo Molnar. This patch allows nearly all of the kernel to be preempted, with the exception of a few very small regions of code ("raw_spinlock critical regions"). This is done by replacing most kernel spinlocks with mutexes that support priority inheritance, as well as moving all interrupt and software interrupts to kernel threads.
You can find now a detailed RT_PREEMPT_HOWTO on this page.
Paul McKenney has written a good CONFIG_PREEMPT_RT overview which is a good introduction to the changes introduced to the kernel by the CONFIG_PREEMPT_RT patch.
The CONFIG_PREEMPT_RT patch set is also maintained in a git repo at kernel.org (rt/* branches).
There is also an apt repository for Ubuntu with x86 precompiled kernel. You can find more information in this wiki page:
Please send patches for the CONFIG_PREEMPT_RT Patch Set to LKML and put Ingo Molnar and Thomas Gleixner on CC.
Please do not send clocksource and clockevents related patches against the -rt patch. Make sure they apply against Linus' tree.
Platforms Tested and in Use with CONFIG_PREEMPT_RT
|Processor||Model #'s||Kernel version(s)||Contact(s)||Comment(s)|
|Opteron||IBM LS21, LS22, HS21XM, HS22x, 3455, 3550, 3650||2.6.16-rt22, 2.6.20-rt8||Theodore Ts'o, Darren Hart||Systems have SMI Remediation support and handle ECC errors via the ibmprtm daemon.|
|Xeon||IBM 6850-P4U||2.6.20-rt8, 2.6.21-rc6-rt0||Dave Sperry|
|Intel Xeon 2.4GHz with HT||HP xw8000||22.214.171.124-rt12||Raphaël Doursenaud|
|AMD Opteron 175||ASUS A8N-SLI Premium||126.96.36.199-rt12||Raphaël Doursenaud|
|P4||Compaq Evo N610||2.6.16-rt22||Dave Sperry|
|P3||Celeron 1300||188.8.131.52-rt14||Oleksandr Natalenko|
|Intel||Pentium Dual-Core T2330||184.108.40.206-rt4||Oleksandr Natalenko|
|Prescott||PentiumD 3 GHz||220.127.116.11-rt9||Dmitry Pisklov|
|Intel||Pentium 4 2.4 GHz||18.104.22.168-rt12||Jaswinder Singh|
|Intel||Pentium 4 2.8 GHz with HT||22.214.171.124-rt12||Jaswinder Singh|
|Intel||FSC D2151S Celeron D 2.93 Ghz||2.6.20-rt8||Remy Bohmer||Avg. latency < 10us, worst case latency: < 30us (see Note 1)|
|Intel||FSC D2151S Core 2 Duo E6300||2.6.20-rt8||Remy Bohmer||Avg. latency < 10us, worst case latency: < 30us (see Note 1)|
|Intel||Asus P5B Core 2 Duo E6600 2.4GHz||2.6.23-rc4-rt1||Remy Bohmer||Avg. latency < 10us, worst case latency: < 30us (see Note 1)|
|Intel||Core 2 Quad Q6600||126.96.36.199-rt27||User:Pauls||Works ok, but frequency scaling has to be turned off for decent results. A task run at 1 kHz repetition rate with low load was found to be t-distributed with 4 degrees of freedom, with 1% value 0.9842 ms, 99% value 1.0103 ms (ideal realtime performance would get exactly 1 ms for both values), with the frequency governor set to "performance".|
|Intel Core 2 Quad Q6600||Gigabyte EP35C-DS3R||188.8.131.52-rt23||Raphaël Doursenaud|
|Intel|| Core 2 Quad Q9000
|2.6.31-5-rt #6-Ubuntu SMP PREEMPT RT x86_64||M A Chojnowski||Seems to work perfectly, but often seeing high userspace lock contentions.|
|Intel||IBM Thinkpad T43 Pentium M CPU 2 GHz||2.6.23-rt3||PhilK||Avg. latency < 14us, worst case latency: < 32us|
|Intel||Pentium 4 (M) 1.8 GHz||184.108.40.206-rt7||Matthias Kaehlcke|
|ARM9 (v4t)||Atmel AT91RM9200-EK (See AT91-Notes)||220.127.116.11-rt14||Remy Bohmer||worst case latency: < 300us (see Note 1)|
|ARM9 (v4t)||FREE_ECB_AT91 (See AT91-Notes)||18.104.22.168-rt14||Carlos Camargo|
|ARM9 (v4t)||Cirrus EP9301||22.214.171.124-rt7||Matthias Kaehlcke|
|ARM9 (v5tej)||Atmel AT91SAM9261 (See AT91-Notes)||126.96.36.199-rt27||Remy Bohmer||worst case latency: < 150us (see Note 1)|
|ARM9 (v5tej)||TI OMAP5912 OSK||2.6.23-rt1||OMAP ML||A small additional OMAP specific patch on top of -rt is needed. See ML.|
|ARM9 (v5tej)||TI DM6446 DaVinci||2.6.23-rt1||DaVinci ML||A small additional DaVinci specific patch on top of -rt is needed. See ML.|
|ARM9 (v5tej)||TS-7800 Marvell MV88F5182 ARM9 500MHz||188.8.131.52-rt13||Stefan Agner||worst case latency: < 250us, see agner.ch (german)|
|SH4||Renesas R2D/R2D+ SH7751R CPU||2.6.21-rt2 and later||linux-sh ML|
Note 1: latency is defined as the time between the moment an interrupt occurs in hardware, and the moment the corresponding interrupt-thread gets running.
AT91-Notes: The following issues are known on this architecture:
- Priority Inheritance Mutexes in userspace (PTHREAD_PRIO_INHERIT) only works since 2.6.23-rt1 with Glibc 2.5 and higher. Tested and stable with applications that match the memory locking scheme described on HOWTO:_Build_an_RT-application.
- Clocksource and clockevent implementations are available, and are in mainline since 2.6.24-rc4. (or see AT91-patchset) Tickless and HRT both work, but not using them due to very high CPU load compared to a ticking kernel on preempt-rt.
- GPIO Interrupt handling is not stable which causes missing GPIO interrupts, fixed by patch. This patch is integrated in 184.108.40.206-rt14 and newer (Without this patch, the Ethernet adapter (DM9000) on AT91SAM9261-EK does not work in combination with PREEMPT-RT.)
Note 2: A wide range of systems and architectures (various x86, ARM, PPC, MIPS) with a PREEMPT_RT patched mainline kernel is continuously tested at the OSADL QA Farm Realtime under idle and load conditions. Both continuous latency monitoring data and cyclictest-generated latency plots are available on-line and updated as soon as new data become available. Here latency is defined as the time between a timer interrupt occurs or, if scheduled by other reasons, a process is enqueued, and the moment the corresponding waiting user-space program is about to be switched to.